In CMOS image sensors an ADC arrangement is used wherein a voltage of each pixel is compared with a ramp voltage. At the point where the ramp voltage equals the pixel voltage, a comparator latches a digital count value into a memory. In this architecture, the resolution of the ADC is directly related to the resolution and linearity of the ramp generation circuitry.
Known ramp generators using ADCs, switched capacitor integrators, charge pumps or the use of current into a capacitor suffer from a number of problems, such as the following: offsets, achieving the necessary gain within the time constants required for settling, area and power inefficiency, non-monotonicity, and process/temperature dependence.
Shift registers in combination with a resistance ladder, as shown in FIG. 1, have also been used as ramp generators. In this arrangement the ramp voltage Vramp is generated by sequentially closing each switch 102 on the resistance ladder 104, thereby tapping the master voltage Vm at different intervals. The sequential closing of the switches is provided by a shift register 106 which has a number of shift register elements 108 corresponding to the number of resistive elements in the resistance ladder 104. The shift register 106 is provided with a clock pulse signal and a token signal where the token signal has a single high pulse. This single high pulse is passed through the shift register elements 108, and thereby closing the respective switches 102 on each clock pulse.
This type of ramp generator can pose a significant problem in terms of physical size since a 12 bit ramp generator requires 2048 shift register elements and 2048 resistive elements. In terms of integrated circuits (ICs), shift register elements are relatively large, requiring a minimum of 8 transistors. This can be prohibitive when IC space is at a premium and the quality of ramp generation is paramount.
Also, shift register elements have been used to control more than one switch, thereby reducing the number of shift register elements required. The methods used have not enabled a reduction in size of the overall ramp generator, but in fact have increased the overall size by using a digital control circuit to control the closing of the switches. This had advantages in other areas but significantly increases the complexity and the physical size of the ramp generator when integrated on an integrated circuit.